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aDual, 12-Bit, 40 MSPS MCM A/D Converterwith Analog Input Signal ConditioningAD10242The AD10242 operates with 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digitalconversion. Each channel is completely independent, allowingoperation with independent encode or analog inputs. The AD10242also offers the user a choice of analog input signal ranges to minimize additional signal conditioning required for multiple functionswithin a single system. The heart of the AD10242 is the AD9042,which is designed specifically for applications requiring widedynamic range.FEATURES2 Matched ADCs with Input Signal ConditioningSelectable Bipolar Input Voltage Range(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)Full MIL-STD-883B Compliant80 dB Spurious-Free Dynamic RangeTrimmed Channel-Channel MatchingAPPLICATIONSRadar ProcessingCommunications ReceiversFLIR ProcessingSecure CommunicationsAny I/Q Signal Processing ApplicationThe AD10242 is manufactured on Analog Devices’MIL-PRF-38534 MCM line and is completely qualified. Unitsare packaged in a custom, cofired, ceramic 68-lead gull wingpackage and specified for operation from –55 C to 125 C.Contact the factory for additional custom options including thosethat allow the user to ac couple the ADC directly, bypassing thefront end amplifier section. Also see the AD9042 data sheet foradditional details on ADC performance.GENERAL DESCRIPTIONThe AD10242 is a complete dual signal chain solution includingon-board amplifiers, references, ADCs, and output bufferingproviding unsurpassed total system performance. Each channel islaser trimmed for gain and offset matching and provides channelto-channel crosstalk performance better than 80 dB. The AD10242utilizes two each of the AD9632, OP279, and AD9042 in a custom MCM to gain space, performance, and cost advantages oversolutions previously available.PRODUCT HIGHLIGHTS1. Guaranteed sample rate of 40 MSPS.2. Dynamic performance specified over entire Nyquist band;spurious signals @ 80 dBc for –1 dBFS input signals.3. Low power dissipation: 2 W off 5.0 V supplies.4. User defined input amplitude.5. Packaged in 68-lead ceramic leaded chip carrier.FUNCTIONAL BLOCK DIAGRAMAIN2AIN3AIN1AIN1AIN2AIN3UNEG UCOM UPOSUPOSOP279OP279AD9632AD9632UCOMUNEGOP279(LSB) 4A12D11B (MSB)AD102421295OUTPUT BUFFERINGD8BD6AD7AD10BD9BOUTPUT BUFFERINGD5A7D7BTIMINGD8AENCREV. DENCD9AD10A D11A(MSB)Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties thatmay result from its use. No license is granted by implication or otherwiseunder any patent or patent rights of Analog Devices. Trademarks andregistered trademarks are the property of their respective companies.D0B(LSB)D1BD2BD3BD4BD5BD6BOne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700www.analog.comFax: 781/461-3113 2015 Analog Devices, Inc. All rights reserved.

AD10242–SPECIFICATIONSElectrical CharacteristicsParameter(AVCC 5 V; AVEE –5.0 V; DVCC 5 V; applies to each ADC, unless otherwise 2BZ/TZTypMax12DC ACCURACYNo Missing CodesOffset ErrorOffset Error Channel MatchGain Error1Gain Error Channel MatchFull25 CFullFull25 CFullFullVIIVIVIVIV1, 2, 312, 3–0.5–2.012, 3–1.0–1.5Guaranteed 0.05 1.0 0.1 0.5 0.8 0.1UnitBits 0.5 2.0 1.0 1.5% FS% FS%% FS% FS%ANALOG INPUT (AIN)Input Voltage RangeAIN1AIN2AIN3Input ResistanceAIN1AIN2AIN3Input Capacitance2Analog Input Bandwidth3FullFullFullIIIFullFullFull25 CFullIVIVIVIVV12121212991983960ENCODE INPUT4, 5Logic CompatibilityLogic “1” VoltageLogic “0” VoltageLogic “1” Current (VINH 5 V)Logic “0” Current (VINL 0 V)Input CapacitanceFullFullFullFull25 CIIIIV1, 2, 31, 2, 31, 2, 31, 2, 3122.00SWITCHING PERFORMANCEMaximum Conversion Rate6Minimum Conversion Rate6Aperture Delay (tA)Aperture Delay MatchingAperture Uncertainty (Jitter)ENCODE Pulsewidth HighENCODE Pulsewidth LowOutput Delay (tOD)FullFull25 C25 C25 C25 C25 CFullVIVVVVIVIVIV4, 5, 612121212101.0 2.0110101225 C25 CFull25 CFull25 CFullVIIIIIIIII45, 645, 645, 663626362605968666665656362dBdBdBdBdBdBdB25 C25 CFull25 CFull25 CFullVIIIIIIIII45, 645, 645, g Input @ 1.2 [email protected] 4.85 [email protected] 9.9 [email protected] 19.5 MHzSINAD8Analog Input @ 1.2 [email protected] 4.85 [email protected] 9.9 [email protected] 19.5 MHz 0.5 1.0 5124114MSPSMSPSnsnsps rmsnsnsnsREV. D

AD10242TempTestLevelMilSubgroupMin25 C25 CFull25 CFull25 CFullIIIIIIIIII45, 645, 645, SdBFSFullII4, 5, 67076dBc25 CIV127580dBTRANSIENT RESPONSE25 CV10nsLINEARITYDifferential Nonlinearity(Encode 20 MHz)Integral Nonlinearity(Encode 20 MHz)25 CFull25 CIVIVVFullVParameterSPURIOUS-FREE DYNAMIC RANGE 9Analog Input @ 1.2 [email protected] 4.85 [email protected] 9.9 [email protected] 19.5 MHzTWO-TONE IMD REJECTION 10F1, F2 @ –7 dBFSCHANNEL-TO-CHANNEL ISOLATIONOVERVOLTAGE RECOVERY TIME 12VIN 2.0 FSVIN 4.0 FSDIGITAL OUTPUTSLogic CompatibilityLogic “1” Voltage13Logic “0” Voltage14Output CodingPOWER SUPPLYAVCC Supply VoltageI (AVCC) CurrentAVEE Supply VoltageI (AVEE) CurrentDVCC Supply VoltageI (DVCC) CurrentICC (Total) Supply CurrentPower Dissipation (Total)Power Supply Rejection Ratio (PSRR)Pass-Band Ripple to 10 II1, 2, 31, 2, 3FullFullFullFullFullFullFullFullVIVVIVVIVII1, 2, 31, 2, 3FullFullIIV7, 8123.5CMOS4.20.450.65Twos AVmAVmAmAW0.020.2% FSR/% VSdBNOTES1Gain tests are performed on A IN3 over specified input voltage range.2Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.3Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.4ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 µF capacitor.5ENCODE may also be driven differentially in conjunction with ENCODE; see Encoding the AD10242 section for details.6Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%.7Analog Input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode 40.0 MSPS.8Analog Input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise harmonics. Encode 40.0 MSPS.9Analog Input signal equals –1 dBFS; SFDR is the ratio of converter full scale to worst spur.10Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 10.0 MHz 100 kHz, 50 kHz f1 – f2 300 kHz.11Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A IN1).12Input driven to 2 and 4 AIN1 range for 4 clock cycles. Output recovers in band in specified time with Encode 40 MSPS. No foldover guaranteed.13Outputs are sourcing 10 µA.14Outputs are sinking 10 µA.All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.Specifications subject to change without notice.REV. D–3–

AD10242ABSOLUTE MAXIMUM RATINGS 1ParameterELECTRICALVCC VoltageVEE VoltageAnalog Input VoltageAnalog Input CurrentDigital Input Voltage (ENCODE)ENCODE, ENCODE Differential VoltageDigital Output CurrentTable I. Output CodingMinMaxUnit0–7VEE–10070VCC 10VCC4 40VVVmAVVmA 125175300 150 C C C 111111111111000000000000Base 10Input2047 10–1, 4095–2047, 2048 FS0.0 V–FSEXPLANATION OF TEST LEVELSTest Level2ENVIRONMENTALOperating Temperature (Case)Maximum Junction TemperatureLead Temperature (Soldering, 10 sec)Storage Temperature Range (Ambient)LSB–55–65I– 100% Production Tested.II – 100% production tested at 25 C, and sample tested atspecified temperatures. AC testing done on sample basis.III – Sample Tested Only.NOTES1Absolute maximum ratings are limiting values to be applied individually, and beyondwhich the serviceability of the circuit may be impaired. Functional operability is notnecessarily implied. Exposure to absolute maximum rating conditions for anextended period of time may affect device reliability.2Typical thermal impedances for ES-68-1 package: θJC 11 C/W; θJA 30 C/W.IV – Parameter is guaranteed by design and characterizationtesting.V – Parameter is a typical value only.VI – All devices are 100% production tested at 25 C; sampletested at temperature extremes.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD10242 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.–4–WARNING!ESD SENSITIVE DEVICEREV. D

NB2AINB1AINA178GNDBAINB3AINA29AVCCGNDAAINA3PIN CONFIGURATION68-Lead Ceramic Leaded Chip Carrier1 68 67 66 65 64 63 62 61GNDA 10PIN 1IDENTIFIERGNDA 11UPOSA 1260GNDBGNDBGNDB57 UPOSB56 UNEGB5958AVEE 13AVCC 14NC 1555UCOMBNC 1654GNDBAD1024253GNDBTOP VIEW(Not to Scale)52ENCODEBENCODEB(LSB) D0A 17D1A 18D2A 1951D3A 2050D4A 2149D5A 2248D6A 2347D7A 2446D8A 2545D8BD7BGNDA 2644GNDBDVCCD11B (MSB)D10BD9BD6BGNDBD5BD3BD4BD1BD2B(LSB) D0B(MSB) D11ANCNCD10AGNDANC NO CONNECTENCODEAENCODEADVCCD9A27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43PIN FUNCTION DESCRIPTIONSPin No.MnemonicFunction12, 5, 9–11, 26–273467812131415, 16, 34, 3517–25, 31–33282930, 5036–42, 45–4943–44, 53–54,58–61, 65, D0B–D11BGNDBInternal Ground Shield between Channels.A Channel Ground. A and B grounds should be connected as close to the device as possible.Unipolar Negative.Unipolar Common.Analog Input for A Side ADC (Nominally 0.5 V).Analog Input for A Side ADC (Nominally 1.0 V).Analog Input for A Side ADC (Nominally 2.0 V).Unipolar Positive.Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).Analog Positive Supply Voltage (Nominally 5.0 V).No Connect.Digital Outputs for ADC A. (D0 LSB.)ENCODE is the complement of ENCODE.Data conversion is initiated on the rising edge of the ENCODE input.Digital Positive Supply Voltage (Nominally 5.0 V).Digital Outputs for ADC B. (D0 LSB.)B Channel Ground. A and B grounds should be connected as close to the deviceas possible.Data conversion is initiated on the rising edge of the ENCODE input.ENCODE is the complement of ENCODE.Unipolar Common.Unipolar Negative.Unipolar Positive.Analog Input for B Side ADC (Nominally 0.5 V).Analog Input for B Side ADC (Nominally 1.0 V).Analog Input for B Side ADC (Nominally 2.0 V).Analog Positive Supply Voltage (Nominally 5.0 V).Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).REV. VEE–5–

AD10242Overvoltage Recovery TimeDEFINITION OF SPECIFICATIONSAnalog BandwidthThe amount of time required for the converter to recover to0.02% accuracy after an analog input signal of the specifiedpercentage of full scale is reduced to midscale.The analog input frequency at which the spectral power of thefundamental frequency (as determined by the FFT analysis) isreduced by 3 dB.Power Supply Rejection RatioThe ratio of a change in input offset voltage to a change in powersupply voltage.Aperture DelayThe delay between the 50% point of the rising edge of theENCODE command and the instant at which the analog inputis sampled.Signal-to-Noise and Distortion (SINAD)The sample-to-sample variation in aperture delay.The ratio of the rms signal amplitude (set at 1 dB below fullscale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.Differential NonlinearitySignal-to-Noise Ratio (SNR, without Harmonics)The deviation of any code from an ideal 1 LSB step.The ratio of the rms signal amplitude (set at 1 dB below fullscale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.Aperture Uncertainty (Jitter)Encode Pulsewidth/Duty CyclePulsewidth high is the minimum amount of time that theENCODE pulse should be left in Logic “1” state to achieve ratedperformance; pulsewidth low is the minimum time that theENCODE pulse should be left in low state. At a given clockrate, these specifications define an acceptable encode duty cycle.Harmonic DistortionThe ratio of the rms signal amplitude to the rms value of theworst harmonic component.Spurious-Free Dynamic Range (SFDR)The ratio of the rms signal amplitude to the rms value of thepeak spurious spectral component. The peak spurious component may or may not be a harmonic. SFDR may be reported indBc (i.e., degrades as signal levels are lowered) or in dBFS(always related back to converter full scale).Transient ResponseThe time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to theanalog input.Integral NonlinearityThe deviation of the transfer function from a reference linemeasured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.Two-Tone Intermodulation Distortion RejectionThe ratio of the rms value of either input tone to the rms value ofthe worst third order intermodulation product; reported in dBc.Minimum Conversion RateThe encode rate at which the SNR of the lowest analog signalfrequency drops by no more than 3 dB below the guaranteed limit.Two-Tone SFDRThe ratio of the rms value of either input tone to the rms value ofthe peak spurious component. The peak spurious componentmay or may not be an IMD product. Two-tone SFDR may bereported in dBc (i.e., degrades as signal levels are lowered) orin dBFS (always related back to converter full scale).Maximum Conversion RateThe encode rate at which parametric testing is performed.Output Propagation DelayThe delay between the 50% point of the rising edge of the ENCODEcommand and the time when all output data bits are within validlogic levels.–6–REV. D

AD10242N 1NN 2N 3N 4N 5ENCTTL CLOCKf 10MHzD11D10D9D8D7D6D5D4D3D2D1D0ENCAINAIN3tA 1.0ns TYP1/2AD10242SHOWNAIN2ENCODEAIN1tOD 12ns TYPDIGITALOUTPUTSN–2N–1NN 1N 2ALL 5V SUPPLY PINS BYPASSEDTO GND WITH A 0.1 F CAPACITORFigure 2. Equivalent Burn-In CircuitFigure 1. Timing DiagramEQUIVALENT CIRCUITSDVCCAIN3AIN2R4200 CURRENTMIRRORR3100 AIN1R221 TO AD9632R179 DVCCVREFFigure 3. Analog Input StageD0–D11AVCCAVCCR117k R117k AVCCCURRENTMIRRORENCODEENCODER28k TIMINGCIRCUITSR28k Figure 5. Digital Output StageFigure 4. Encode InputsREV. D–7–

AD10242–Typical Performance Characteristics0ENCODE 40MSPSAIN 4.85MHzAIN –1dBFSSNR 66.4dBSFDR 72.8dBc–10–20POWER RELATIVE TO FULL SCALE – dBPOWER RELATIVE TO FULL SCALE – 1214FREQUENCY – MHz1618AIN2 10.1MHzAIN2 –7dBFSSFDR 76.0dBc–30–40–50–60–70–80–90020TPC 1. Single Tone @ 4.85 MHz2460–20POWER RELATIVE TO FULL SCALE – dBENCODE 40MSPSAIN 9.9MHzAIN –1dBFSSNR 66.0dBSFDR 8101214FREQUENCY – 214FREQUENCY – MHz16182076ENCODE 40MSPSAIN 19.5MHzAIN –1dBFSSNR 64.3dBSFDR 63.3dBcENCODE 40MSPSAIN –1dBFS74WORST-CASE HARMONIC – dB–3020TPC 5. Two-Tone FFT @ 19.5 MHz/19.7 MHz0–2018–4020TPC 2. Single Tone @ 9.9 MHz–1016ENCODE 40MSPSAIN1 19.5MHzAIN1 –7dBFSAIN2 19.7MHzAIN2 –7dBFSSFDR 70.6dBc–10–100–10008101214FREQUENCY – MHzTPC 4. Two-Tone FFT @ 9.8 MHz/10.1 MHz0POWER RELATIVE TO FULL SCALE – dB–20–1000POWER RELATIVE TO FULL SCALE – dBENCODE 40MSPSAIN1 9.8MHzAIN1 –7dBFS–10–40–50–60–70–807270T 125 C68T 25 C66T –55 C646260–90–10002468101214FREQUENCY – MHz16185820510ANALOG INPUT FREQUENCY – MHz20TPC 6. Harmonics vs. AINTPC 3. Single Tone @ 19.5 MHz–8–REV. D

AD1024267.0–90IN A166.5IN B1–80T –55 C66.0–7065.5IN B3ISOLATION – dBT 25 CSNR – dB65.064.5T 125 C64.063.5ENCODE 40MSPSAIN ANALOG INPUT FREQUENCY – MHz52068WORST-CASE SPURIOUS – dBc, dBFSAIN 9.9MHzAIN –1dBFSSNR, WORST SPUR – dB, dBc20253035ANALOG INPUT FREQUENCY – MHz409070SFDR66SNR6462605101520253035SAMPLE RATE – MSPS404550SFDR (dBFS)706050SFDR (dBc)40SFDR 75dB3020ENCODE 40MSPSAIN 9.98MHz10–60–50–40–30–20–10ANALOG INPUT POWER LEVEL – dBFS0TPC 11. Single Tone SFDR (AIN @ 9.98) vs. Power LevelTPC 8. SNR and Harmonics vs. Encode Rate2.0WORST-CASE SPURIOUS – dBc, 0–55800–7058ERROR – % FS15TPC 10. Isolation vs. FrequencyTPC 7. SNR vs. AIN9080SFDR (dBFS)7060SFDR (dBc)5040SFDR 75dB3020ENCODE 40MSPSAIN E – C–60–50–40–30–20–10ANALOG INPUT POWER LEVEL – dBFS0TPC 12. Single Tone SFDR (AIN @ 19.9) vs. Power LevelTPC 9. Offset and Gain Error vs. TemperatureREV. DENCODE 40MSPSAIN –1dBFS–2062.5IN A3–9–

AD1024280–0.5700ENCODE 40MSPSFUNDAMENTAL LEVELS – dBFSSNR, WORST SPUR – dB, dBcSNR (dB)6050SFDR (dBFS)403020ENCODE 40MSPSAIN 1dBFS100.51.01.52.02.53.005102029.234.552.5ANALOG INPUT FREQUENCY – MHz060.95TPC 13. SNR/Harmonics to AIN Nyquist MSPS510152025303540INPUT FREQUENCY – MHz455055TPC 14. Gain Flatness vs. Input FrequencyTHEORY OF OPERATIONRefer to the functional block diagram. The AD10242 employsthree monolithic ADI components per channel (AD9632, OP279,and AD9042), along with multiple passive resistor networksand decoupling capacitors to fully integrate a complete 12-bitanalog-to-digital converter.APPLYING THE AD10242Encoding the AD10242The AD10242 is designed to interface with TTL and CMOSlogic families. The source used to drive the ENCODE pin(s)must be clean and free from jitter. Sources with excessive jitterwill limit SNR and overall performance.The input signal is first passed through a precision laser trimmedresistor divider, allowing the user to externally select operationwith a full-scale signal of 0.5 V, 1.0 V, or 2.0 V by choosingthe proper input terminal for the application. The result ofthe resistor divider is to apply a full-scale input of approximately0.4 V to the noninverting input of the internal AD9632 amplifier.The AD9632 provides the dc-coupled level shift circuit requiredfor operation with the AD9042 ADC. Configuring the amplifierin a noninverting mode, the ac signal gain can be trimmed toprovide a constant input to the ADC centered around the internal reference voltage of the AD9042. This allows the converterto be used in multiple system applications without the need forexternal gain and level shift circuitry normally requiring trim.The AD9632 was chosen for its superior ac performance andinput drive capabilities. These two specifications have limitedthe ability of many amplifiers to drive high performance ADCs.As new amplifiers are developed, pin compatible improvements are planned to incorporate the latest operational amplifier technology.The OP279 provides the buffer and inversion of the internalreference of the AD9042 in order to supply the summing nodeof the AD9632 input amplifier. This dc voltage is then summedwith the input voltage and applied to the input of the AD9042ADC. The reference voltage of the AD9042 is designed to trackinternal offsets and drifts of the ADC and is used to ensurematching over an extended temperature range of operation.AD10242TTL OR CMOSSOURCEENCODEENCODE0.01 FFigure 6. Single-Ended TTL/CMOS EncodeThe AD10242 encode inputs are connected to a differentialinput stage (see Figure 4). With no input connected to eitherthe ENCODE or ENCODE input, the voltage dividers bias theinputs to 1.6 V. For TTL or CMOS usage, the encode sourceshould be connected to ENCODE (Pins 29 and/or 51). ENCODE(Pins 28 and/or 52) should be decoupled using a low inductanceor microwave chip capacitor to ground. Devices such as AVX05085C103MA15, a 0.01 µF capacitor, work well.Performance ImprovementsIt is possible to improve the performance of the AD10242slightly by taking advantage of the internal characteristics of theamplifier and converter combination. By increasing the 5 Vsupply slightly, the user may be able to gain up to a 5 dB improvement in SFDR over the entire frequency range of the converter.It is not recommended to exceed 5.5 V on the analog suppliessince there are no performance benefits beyond that range andcare should be taken to avoid the absolute maximum ratings.–10–REV. D

AD10242If a logic threshold other than the nominal 1.6 V is required,the following equations show how to use an external resistor,Rx, to raise or lower the trip point (see Figure 4, R1 17 kΩ,R2 8 kΩ).V1 5R2Rxto lower logic threshold.R1R2 R1Rx R2RxENCODESOURCEENCODEVl0.01 FIf no TTL source is available, a clean sine wave may be substituted. In the case of the sine source, the matching network isshown below. Since the matching transformer specified is a 1:1impedance ratio, the load resistor R should be selected to matchthe source impedance. The input impedance of the AD9042is negligible in most e 10. Sine Source—Differential EncodeFigure 7. Lower Threshold for EncodeV1 T1–1TSINESOURCE5V5R 2to raise logic threshold.R1RxR2 R1 RxIf a low jitter ECL clock is available, another option is to ac-couplea differential ECL signal to the encode input pins, as shownin Figure 11. The capacitors shown here should be chip capacitors but do not need to be of the low inductance variety.0.1 FAVCCENCODEECLGATEAD102420.1 FENCODERxENCODESOURCEENCODEVl0.01 FENCODE5VFigure 11. Differential ECL for EncodeWhile the single-ended encode will work well for many applications, driving the encode differentially will provide increasedperformance. Depending on circuit layout and system noise, a1 dB to 3 dB improvement in SNR can be realized. It is recommended that the encode signal be ac-coupled into the ENCODEand ENCODE pins.The simplest option is shown below. The low jitter TTL signalis coupled with a limiting resistor, typically 100 Ω, to the primaryside of an RF transformer (these transformers are inexpensiveand readily available; part number in Figures 9 and 10 is fromMini-Circuits). The secondary side is connected to the ENCODEand ENCODE pins of the converter. Since both encode inputsare self-biased, no additional components are required.100 T1–1TAs a final alternative, the ECL gate may be replaced by an ECLcomparator. The input to the comparator could then be a logicsignal or a sine signal.AD96687 (1/2)0.1 FENCODEAD102420.1 F50 ENCODE510 510 –VSFigure 12. ECL Comparator for EncodeCare should be taken not to overdrive the encode input pin whenac-coupled. Although the input circuitry is electrically protectedfrom overvoltage or undervoltage conditions, improper circuitoperations may result from overdriving the encode input pin.ENCODEAD10242ENCODEFigure 9. TTL Source—Differential EncodeREV. D510 –VSR2AD10242Figure 8. Raise Logic Threshold for EncodeTTL510 R1–11–

AD10242USING THE FLEXIBLE INPUTThe AD10242 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included onboard to allow the user a choice of input signal levels and inputimpedance. While the standard inputs are 0.5 V, 1.0 V, and 2.0 V, the user can select the input impedance of the AD10242on any input by using the other inputs as alternate locations forGND or an external resistor. The following chart summarizes theimpedance options available at each input location:AIN1 100 Ω when AIN2 and AIN3 are open.AIN1 75 Ω when AIN3 is shorted to GND.AIN1 50 Ω when AIN2 is shorted to GND.AIN2 200 Ω when AIN3 is open.AIN2 100 Ω when AIN3 is shorted to GND.AIN2 75 Ω when AIN2 to AIN3 has an external resistor ofAIN2 300 Ω, with AIN3 shorted to GND.AIN2 50 Ω when AIN2 to AIN3 has an external resistor of AIN2 100 Ω, with AIN3 shorted to GND.AIN3 400 Ω.AIN3 100 Ω when AIN3 has an external resistor of 133 Ω to GND.AIN3 75 Ω when AIN3 has an external resistor of 92 Ω to GND.AIN3 50 Ω when AIN3 has an external resistor of 57 Ω to GND.While the analog inputs of the AD10242 are designed fordc- coupled bipolar inputs, the AD10242 has the ability touse unipolar inputs in a user selectable mode through the addition of an external resistor. This allows for 1 V, 2 V, and 4 Vfull-scale unipolar signals to be applied to the various inputs(AIN1, AIN2, and AIN3, respectively). Placing a 2.43 kΩ resistor (typical, offset calibration required) between UPOS andUCOM shifts the reference voltage setpoint to allow a unipolarpositive voltage to be applied at the inputs of the device. To calibrate offset, apply a midscale dc voltage to the converter whileadjusting the unipolar resistor for a midscale output transition.A IN 1A IN 2A IN 3UPOSA IN 1A IN 2A IN 3UNEGAD102422.67k UCOMFigure 14. Unipolar NegativeGROUNDING AND DECOUPLINGAnalog and Digital GroundingProper grounding is essential in any high speed, high resolutionsystem. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. Theuse of ground and power planes offers distinct advantages:1. The minimization of the loop area encompassed by a signaland its return path.2. The minimization of the impedance associated with groundand power paths.3. The inherent distributed capacitor formed by the powerplane, PCB insulation, and ground plane.These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement inperformance.It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run inparallel with input signal traces and should be routed away fromthe input circuitry. The AD10242 does not distinguish betweenanalog and digital ground pins as the AD10242 should alwaysbe treated like an analog component. All ground pins should beconnected together directly under the AD10242. The PCBshould have a ground plane covering all unused portions of thecomponent side of the board to provide a low impedance pathand manage the power and ground currents. The ground planeshould be removed from the area near the input pins to reducestray capacitance.AD10242LAYOUT INFORMATION2.43k UCOMFigure 13. Unipolar PositiveTo operate with –1 V, –2 V, or –4 V full-scale unipolar signals,place a 2.67 kΩ resistor (typical, offset calibration required)between UNEG and UCOM. This again shifts the reference voltage setpoint to allow a unipolar negative voltage to be applied atthe inputs of the device. To calibrate offset, apply a midscale dcvoltage to the converter while adjusting the unipolar resistor fora midscale output transition.The schematic of the evaluation board (Figure 15) represents atypical implementation of the AD10242. The pinout of theAD10242 is very straightforward and facilitates ease of useand the implementation of high frequency/high resolutiondesign practices. It is recommended that high quality ceramicchip capacitors be used to decouple each supply pin to grounddirectly at the device. All capacitors except the one placed onENCODE can be standard high quality ceramic chip capacitors.The capacitor used on the ENCODE pin must be a low inductance chip capacitor as referenced previously.–12–REV. D

AD102425VAC10.1 FU1K1115SMA SMAJ1JA14VCCVEEU5AD9696KN82R9470 3R10470 U2K1115175VAC140.1 F5VA51 H2DME5J1712T1T1–1T43SMAJ11PULSE BINPULSE AOUT6SMAJ13SMAJ121VEEU5AD9696KN8251 H2DMJ1812E53C50.1 F56GNDR849.9 5PULSE BOUTB JACKSSMAJ14E1 5VA 5VA–5.2VE4E3GNDGNDVLOWVLOW–5.2V VHIGHVHIGHE2VLOWR5470 R6470 R4470 VHIGHU4C220.1 FU3C210.1 FU3C190.1 FU4C200.1µF 5VU4C170.1 FU3C180.1 FDUTC90.1 FC2310 FU5C120.1 FU6C30.1 FDUTC80.1 FU3C150.1 FU4C160.1 FC2410 FDUTC100.1 FU5C130.1 FU6C40.1 FDUTC110.1 FDUTC70.1 FC2510 FDUTC60.1 FD3AD2AD1A(LSB) D0AGNDGNDGNDGNDGND NB3GNDA IN A3A IN A2A IN A1GNDTP5TP6GNDGNDGND–5.2V 5VAGNDA IN B3A IN B2A IN B1GNDAINA1SMAJ412131415161718192021222324252654321 68 67 66 65 64 63 62 61GNDAGNDAUNIPOSA–5.2VAA 5VAANCANCAD0A DBGNDBUNIPOSBUNINEGBUNICOMBGNDBGNDBENCBENCB 5VDB(MSBB) D11BD10BD9BD8BD7BGNDB27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43Figure 15. Evaluation Board SchematicREV. DGNDB6ENCAENCA 5VDAD9AD10AD11A (MSBA)NCBNCBD0B (LSBB)D1BD2BD3BD4BD5BD6BGNDB117GNDENCAENCA 5VDD9AD10AD11AGNDGNDD0BD1BD2BD3BD4BD5BD6BGND4) POWER (5VD) FOR DIGITAL OUTPUTS OF THEAD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10(THE DIGITAL INTERFACES). TO POWER THE EVAL.BOARD WITH ONE 5V SUPPLY, JUMPER A WIREFROM E1 TO E4 (CONNECTED AT FACTORY).10GNDAGNDGNDTP1–5.2V2) ABOVE UNIPOLAR RESISTOR VALUES ARE 5VANOMINAL AND MAY HAVE TO BE ADJUSTEDGNDDEPENDING ON OFFSET OF DUT.GNDD0A3) ENCODE SOURCESD1AA) FOR NORMAL OPERATION, A 40MHz TTL CLOCKOSCILLATOR IS INSTALLED IN U1 AND U2. THERE D2AD3AIS A 51 RESISTOR BETWEEN J15 AND J16.J17 AND J18 ARE OPEN.D4AB) FOR EXTERNAL SQUARE WAVE ENCODE, INPUTD5ASIGNAL AT J1 AND J8, REMOVE U1, U2, JUMPERS D6AJ15 AND J16. CONNECT JUMPERS J17 AND J18.D7AC) FOR EXTERNAL SINE WAVE ENCODE, INPUTD8ASIGNAL AT J1 AND J8, REMOVE U1, U2, R9, R11,GNDJUMPERS J15 AND J16.CONNECT JUMPERS J17 AND J18.8GNDAA IN A3A IN A2A IN A1GNDAUNICOMAUNINEGAGNDASHIELDGNDB–5.2VAB 5VABGNDBA IN B3A IN B2A IN B19NOTES;1) UNIPOLAR OPERATIONA SIDE CONNECT 2.43k RES. FROM TP1 TO TP5.A SIDE – CONNECT 2.67k RES. FROM TP5 TO TP6.B SIDE CONNECT 2.43k RES. FROM TP2 TO TP4.B SIDE – CONNECT 2.67k RES. FROM TP4 TO TP3.5VD(MSB) LOW1ENCA6T2T1–1T43–13–60595857565554

AV CC Supply Voltage Full VI 5.0 V I (AV CC) Current Full V 260 mA AV EE Supply Voltage Full VI –5.0 V I (AV EE) Current Full V 55 mA DV CC Supply Voltage Full VI 5.0 V I (DV CC) Current Full V 25 mA I CC (Total) Supply Current Full I 1, 2, 3 350 4